The present invention relates to a semiconductor device, and particularly, to a semiconductor device having a heterojunction.
Silicon carbide has one digit larger dielectric breakdown strength than silicon and is processible by thermal oxidization like silicon. Due to this, silicon carbide is drawing attention as a next generation semiconductor material. In particular, silicon carbide is expected for application to power conversion devices. Recently those devices made of silicon carbide are high-withstand-voltage, low-loss power transistors. To reduce a loss from a power transistor, the ON-resistance of the power transistor must be lowered.
As an example of an ON-resistance reduced power transistor, Japanese Laid-Open Patent Publication No. 2003-218398 discloses a field-effect transistor. The disclosed field-effect transistor includes a hetero-semiconductor region and a silicon carbide epitaxial layer that form a heterojunction. The disclosure changes the barrier height of the heterojunction according to an electric field from a gate electrode, to realize a switching operation. This disclosure involves no channel region that is present in, for example, a MOS-type electric-field transistor, and therefore, causes no channel-region voltage drop. With this, the disclosure can reduce ON-resistance. When a high voltage is applied between a source electrode and a drain electrode, an accumulation layer formed on the hetero-semiconductor region side of a heterojunction interface terminates an electric field, so that substantially no electric field reaches the hetero-semiconductor region. As a result, the hetero-semiconductor region causes no breakdown, and a high withstand voltage is secured between the source electrode and the drain electrode.